EDA and IP Cadence gets Incisive to meet verification challenge

EDA and IP Cadence gets Incisive to meet verification challenge

2014/01/14

Cadence Design Systems has introduced a new version of the Incisive functional verification platform,which addresses growing challenge of verification system-on-chip (SoC) devices with multiple IP.

The Incisive 13.2 platform is faster and additional automation features to speed SoC verification closure.

“New Trident engine in the Incisive Formal Verifier and the Incisive Enterprise Verifier, which improves formal analysis performance up to x20,” said Cadence.

“A new constraint engine in the Incisive Enterprise Simulator that speeds UVM and SystemVerilog testbench simulation, and simulation acceleration with the Palladium platform by up to x10,” said the firm.

There is also SystemVerilog support in the debug analyser.

“New support for SystemVerilog IEEE 1800-2012 real number modeling in the Incisive Digital Mixed Signal option for faster mixed-signal simulation over x100,” said Cadence.

“Verification engineers are pressed for time and need strong verification performance. Incisive 13.2 delivers this but also goes beyond raw clocks per second to encompass capabilities from formal apps, debug, and metric aggregation in order to speed verification closure,” said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence.

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