2013年7月14日星期日

Manufacturing UMC tapes out 14nm test chip

Manufacturing UMC tapes out 14nm test chip


34736_ 193Synopsys and UMC have taped out a 14nm test chip.

This process test IC will provide early silicon data, enabling UMC to tune its 14-nm FinFET process and Synopsys to refine its DesignWare IP portfolio for optimal power, performance and area.

It also provides data to enable better correlation of the FinFET simulation models to the silicon results. This is the first milestone of an ongoing collaboration to validate UMC’s 14-nm FinFET processes using DesignWare IP solutions.

Synopsys’ DesignWare Logic Library IP portfolio consists of high-speed, high-density and low-power standard cell libraries that include multiple voltage threshold implementations and support multi-channel gate lengths to minimize leakage power.

Power Optimization Kits (POKs) and Engineering Change Order (ECO) Kits help deliver optimal performance.

Synopsys’ StarRC parasitic extraction tool offers advanced extraction capabilities at 14 nm, based on precise 3-D modeling of the new parasitics found in FinFET devices.

Due to its ability to describe the exact silicon profile of FinFET transistors, StarRC’s embedded field solver generates device model parasitics which enable 14-nm IP developers to optimize their designs for maximum performance and lowest power.

Synopsys’ Galaxy Implementation Platform also provides designers with a full suite of implementation tools that are FinFET-ready.

“Our collaboration with UMC further demonstrates our mutual commitment to delivering proven IP and tools that help designers lower integration risk and speed their time-to-volume production,” says Synopsys’ John Koeter (pictured).

See also: ARM and Synopsys tape out Mali graphics chip on 20nm


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